Highly Stable Reconfigurable TERO PUF Architecture for Hardware Security Applications

IF 3.1 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-07-24 DOI:10.1109/TVLSI.2025.3587502

Kevin Vicuña;Massimo Vatalaro;Frédéric Amiel;Felice Crupi;Lionel Trojman

{"title":"Highly Stable Reconfigurable TERO PUF Architecture for Hardware Security Applications","authors":"Kevin Vicuña;Massimo Vatalaro;Frédéric Amiel;Felice Crupi;Lionel Trojman","doi":"10.1109/TVLSI.2025.3587502","DOIUrl":null,"url":null,"abstract":"This work introduces a novel 128-bit transient effect ring oscillator (TERO)-based physically unclonable function (PUF) designed for Intel MAX 10 field-programmable gate arrays (FPGAs). A reliable PUF solution suitable for security applications targeting high stability and area efficiency is presented. The proposed cell consists of two cross-coupled reconfigurable ring oscillators (ROs) aiming to achieve zero-observed instability at both golden key (GK) and under temperature variations. Conversely to the conventional application-specific integrated circuits (ASIC) approaches, which use the mean cycles to collapse (CTC), here the calibration process was performed by considering the CTC standard deviation extracted at GK conditions, namely, 1.2 V and <inline-formula> <tex-math>$25~^{\\circ }$ </tex-math></inline-formula>C. The experimental results demonstrate that after the calibration process and considering a 1.64% of masked bits, the proposed solution shows a bit error rate (BER) lower than <inline-formula> <tex-math>$\\mathbf {1.56\\times 10^{-4}\\%}$ </tex-math></inline-formula>, the minimum observable quantity for the adopted statistical set across the entire analyzed temperature range. Further, the solution also shows an excellent uniqueness of 49.78%, close to the ideal value of 50%. This is achieved at the cost of two logic array blocks (LABs) per bit.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 10","pages":"2873-2882"},"PeriodicalIF":3.1000,"publicationDate":"2025-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11095825","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/11095825/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}

引用次数: 0

Abstract

This work introduces a novel 128-bit transient effect ring oscillator (TERO)-based physically unclonable function (PUF) designed for Intel MAX 10 field-programmable gate arrays (FPGAs). A reliable PUF solution suitable for security applications targeting high stability and area efficiency is presented. The proposed cell consists of two cross-coupled reconfigurable ring oscillators (ROs) aiming to achieve zero-observed instability at both golden key (GK) and under temperature variations. Conversely to the conventional application-specific integrated circuits (ASIC) approaches, which use the mean cycles to collapse (CTC), here the calibration process was performed by considering the CTC standard deviation extracted at GK conditions, namely, 1.2 V and

$25~^{\circ }$

C. The experimental results demonstrate that after the calibration process and considering a 1.64% of masked bits, the proposed solution shows a bit error rate (BER) lower than

$\mathbf {1.56\times 10^{-4}\%}$

, the minimum observable quantity for the adopted statistical set across the entire analyzed temperature range. Further, the solution also shows an excellent uniqueness of 49.78%, close to the ideal value of 50%. This is achieved at the cost of two logic array blocks (LABs) per bit.

查看原文本刊更多论文

用于硬件安全应用的高度稳定可重构TERO PUF架构

本文介绍了一种新的基于128位瞬态效应环振荡器（TERO）的物理不可克隆功能（PUF），该功能专为Intel MAX 10现场可编程门阵列（fpga）设计。提出了一种可靠的PUF解决方案，适用于高稳定性和区域效率的安全应用。该电池由两个交叉耦合的可重构环形振荡器（ROs）组成，旨在在金钥匙（GK）和温度变化下实现零观察不稳定性。与传统的应用专用集成电路（ASIC）方法使用平均周期折叠（CTC）相反，本文的校准过程考虑了在GK条件下提取的CTC标准偏差，即1.2 V和$25~^{\circ}$ c。实验结果表明，经过校准过程并考虑1.64%的掩码位，所提出的解决方案的误码率（BER）低于$\mathbf{1.56\ \乘以10^{-4}\%}$。所采用的统计集在整个分析温度范围内的最小可观测量。此外，该方案还显示出49.78%的优异唯一性，接近50%的理想值。这是以每比特两个逻辑阵列块（lab）为代价实现的。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.