Modeling and experimental research on the front edge chipping characteristics of dicing monocrystalline silicon with ultra-thin diamond dicing blades

Abstract

Monocrystalline silicon is crucial for manufacturing integrated circuits in modern electronics. Dicing is a key semiconductor fabrication step that improves production efficiency, reduces material waste, and ensures chip conformity. Ultra-thin diamond dicing blades are preferred for dicing monocrystalline silicon wafers due to their exceptional precision and efficiency in producing high-quality chips with minimal material waste and damage. However, the material removal mechanism during the dicing of hard and brittle semiconductor materials remains unclear. This study presents a comprehensive front edge chipping (FEC) model to predict the motion trajectory of diamond abrasive grains, grinding force, crack length, and chipping width during monocrystalline silicon dicing. The models reveal that dicing parameters affect chipping quality by altering the grinding force of diamond grains and lateral crack propagation, thus changing the chipping width. To verify these models, ultra-micro-scale dicing experiments were conducted using self-developed ultra-thin diamond blades. The experimental results are analyzed to derive empirical formulas and variation laws of chipping width with respect to process parameters. This study shows the key role of dicing parameters in surface quality and offers a foundation for optimizing dicing quality. It addresses chipping width control challenges, meeting modern semiconductor manufacturing requirements for precision, efficiency, and quality. The findings deepen the understanding of material behavior during dicing hard and brittle materials, benefiting the advancement of ultra-micro-scale monocrystalline silicon dicing. They provide a foundation for future work in this field.