Self-calibrated comparator and capacitor DAC design for high-precision SAR-ADC

Abstract

This paper introduces a self-calibration architecture for a 12-bit successive approximation register (SAR) analog-to-digital converter (ADC). Single-ended SAR ADCs often encounter challenges such as comparator offset voltage and mismatch in the capacitive digital-to-analog converter (CDAC), which can significantly degrade the overall performance. To address these issues, the proposed ADC employs a self-calibration technique that compensates for comparator offset and DAC mismatch. The comparator calibration is realized using the metal oxide semiconductor (MOS) capacitors, and the DAC mismatch is corrected with an additional calibration DAC. The proposed 12-bit SAR ADC is designed and implemented in complementary metal oxide semiconductor (CMOS) 55 nm library using Cadence Virtuoso design suite. The self-calibration technique significantly enhances ADC performance, increasing the effective number of bits (ENOB) from 9.23 to 10.89 compared to the conventional SAR ADC. It also achieves a differential nonlinearity (DNL) of + 0.53/-0.51 LSB and an integral nonlinearity (INL) of + 0.024/-1.73 LSB, at sampling rate of 17.8 MS/s. The proposed architecture consumes an average power of 7.9µW, while occupies an active area of 0.077\(\:m{m}^{2}\).