Study on the interface interaction between the chip backside metallization and solder alloys of power semiconductor modules

Abstract

Power semiconductor modules are the core device of the electrical power conversion system, whose chip-solder interface is one of the weak points that can cause module failure, requiring an in-depth investigation. In this work, the effect of chip backside metallization (BSM), solder alloy, and solder condition on the interface reaction during reflow soldering was investigated. The interface bonding performance was further evaluated via accelerated aging tests like HTS (High temperature storage) and HTRB (High humidity, high temperature reverse biased). Results show that when the chip BSM of the Al–Ti–Ni–Ag reacted with Sn-based solders, it formed (Cu, Ni)₆Sn₅ intermetallic compound (IMC) with the SAC305 solder, whereas with SnSb5, it probably yielded (Cu, Ni)₆(Sn, Sb)₅. An overly thin initial Ni layer of chip BSM became depleted during the reaction, resulting in a discontinuous interface IMC layer and the dewetting between the Ti layer and IMCs. This discontinuity is more pronounced when SnSb5 solder is employed. A thicker Ni layer can ensure a continuous interface IMC layer and a higher interface bonding strength, though it leads to more interface Kirkendall voids. Increasing solder temperature and time can promote IMCs to dissolve into the solder melt, resulting in the IMC layer drifting into the solder interior. The HTS test can facilitate IMC growth and decrease interface strength, without accompanying IMC phase transformation. Delamination occurred at the interface employed the thin initial Ni layer during the HTRB test, evidencing that the inappropriate chip BSM-solder matching reduces interface reliability.