Rim Amdouni , Mahdi Madani , Mohamed Ali Hajjaji , El Bay Bourennane , Mohamed Atri
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引用次数: 0
Abstract
In today's interconnected world, securing digital image transmissions is crucial to protect sensitive information against modern cyber threats. This paper presents a hardware implementation of a novel chaos-based symmetric cryptosystem for secure grayscale image transmission. The proposed method integrates a 4D Rössler hyperchaotic system as a key generator with a lightweight 128-bit block cipher comprising whitening, pixel-bit permutation, block-pixel permutation, and chaos-based S-box substitution. Both the key generator and the encryption engine are implemented on a Xilinx Virtex UltraScale VCU108 FPGA using VHDL.
The proposed chaotic PRNG successfully passes the NIST SP 800-22 statistical tests, demonstrating strong randomness properties. Experimental results show that the cryptosystem achieves high security and robust resistance to statistical and differential attacks, with entropy values up to 7.9997, NPCR average of 99.62 %, and UACI equal to 33.4 %. The hardware implementation achieves a throughput of 3.49 Gbps with low power consumption of 0.098 W, confirming its suitability for real-time embedded image encryption applications. These results validate the effectiveness of the proposed design in meeting high-speed, low-power, and high-security requirements for modern image transmission systems.
期刊介绍:
Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics:
Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.