Parity generator-checker based nano communication network using reversible quantum majority voter

Abstract

Quantum computing has emerged as a transformative paradigm with profound implications for computation, communication, encryption, and information theory. As classical systems approach their miniaturization and energy-efficiency limits, quantum technologies offer new mechanisms rooted in superposition, entanglement, and reversibility. This paper introduces a foundational nanocommunication framework that integrates three known reversible circuit primitives—majority voter, parity generator, and parity checker—into a unified communication system. Unlike prior works that analyze these circuits in isolation, the proposed architecture validates their combined functionality on the IBM Quantum platform, tested under both ideal (Aer simulator) and realistic noisy (NISQ hardware) conditions. By incorporating depolarizing noise models, mid-circuit resets, and hardware execution, the framework directly reflects the physical constraints of real devices, including qubit errors, decoherence, and relaxation effects. Simulation and hardware results demonstrate system-level fidelity, circuit cost, and accuracy for both small- and higher-bit counts. Comparative analysis with existing teleportation- and entanglement-based protocols highlights the efficiency and scalability of the approach. Overall, this study establishes a practical and foundational step toward noise-resilient, parity-based quantum communication systems, paving the way for larger processor-scale designs in the future.