Layer-dependent performance analysis of black phosphorus Double-Gate TFETs for optimized nanoelectronic applications

Abstract

This work provides a thorough performance evaluation of a Black Phosphorus Double-Gate Tunnel Field-Effect Transistor (BP-DG-TFET) by varying the number of Black Phosphorus (BP) layers from monolayer (1L) to five layers (5L). At a constant drain voltage (V_DS = 1 V), extensive TCAD-based simulations were conducted to analyze important device metrics throughout the DC, analog, radio-frequency (RF), linearity, and harmonic distortion analysis. Despite prior research on Black Phosphorus TFETs, the majority of studies have only examined their DC properties, generally ignoring their analog, RF, linearity, and harmonic distortion behaviour. By methodically examining DC, analog, RF, linearity, and harmonic distortion factors, this work fills this gap and determines the most appropriate BP layer thickness for optimized device performance. As layer thickness increases, DC analysis shows an increase in ON-state current, which is explained by a smaller bandgap and better tunnelling efficiency. Thicker layers result in a significant improvement in analog parameters, including transconductance (g_m), output resistance (R_out), and intrinsic gain (A_V); 4L and 5L architectures have improved gain characteristics. RF figures of merit, such as the 5L device's cut-off frequency (f_T) and gain-bandwidth product (GBW) peak, show outstanding high-frequency performance. The 4L arrangement, however, provides the finest balance between gain, linearity, and signal fidelity, according to a review of harmonic distortion measures (HD₂, HD₃, and THD) and linearity indications (g_m2, g_m3, VIP₂, VIP₃, IIP₃, IMD₃, and P1dB). According to the study's findings, the 4-layer BP-DG-TFET offers the optimized overall performance, making it a viable option for high-performance, low-power biomedical and Internet of Things applications. Furthermore, we look into how realistic oxide scaling affects the performance of BP-DG-TFET. While electrostatic control is maximized by ultra-thin oxides (≈0.59 nm), the study shows that ≈3 nm SiO₂ offers the optimum compromise between ON-current, subthreshold swing, and leakage, guaranteeing both technological viability and robust device performance.