A quality-configurable approximate cache design based on NAND-like SOT MRAM with high energy efficiency

Abstract

Approximate computing is widely used for decreasing the power and area consumption of a system since there are many error-tolerant multimedia applications nowadays. NAND-like spin–orbit torque magnetic tunnel junction (SOT-MTJ) as a novel non-volatile multi-bit memory device with high speed and high area efficiency, has a location-related stochastic switching mechanism, which can achieve 100% accuracy for high significant bits (HSBs) while storing low significant bits (LSBs) approximately through the decrease of writing pulse width. Thus, it is highly suitable for the approximate storage and updating of data. In this work, we proposed a quality-configurable last-level cache based on the NAND-like SOT MRAM by utilizing location-related stochastic switching, where the write pulse width is used as an accuracy knob to switch between precise storage and approximate storage. A highly efficient write operation and a specific pipeline read policy are designed to adapt the novel cell structure and application scenarios. To evaluate the performance of the proposal, a circuit-level simulation model NVSim and a set of approximate computing benchmarks Axbench are utilized. By reducing the writing pulse width of the NAND-like SOT MTJs from 3 ns to 1 ns, the improvement of energy and latency are achieved by 42% and 64% with only 3.4% accuracy loss on average for image processing benchmarks.