{"title":"Few-shot learning GNN-EQL model with gm/ID method for analog integrated circuit design","authors":"Xin Xiong, Hongjian Zhou, Pingqiang Zhou","doi":"10.1016/j.vlsi.2025.102551","DOIUrl":null,"url":null,"abstract":"<div><div>Analog integrated circuit design typically involves extensive analytical derivations to evaluate circuit performance metrics. Although SPICE simulations facilitate efficient prediction of these metrics, the simulation process remains time-consuming as the dimensionality of circuit parameters increases. In this article, we propose integrating Graph Neural Networks (GNN) with Equation Learner Networks (EQL), employing them as pretrained models within a limited range of design parameters. Our results demonstrate that datasets constructed using the <span><math><mrow><msub><mrow><mi>g</mi></mrow><mrow><mi>m</mi></mrow></msub><mo>/</mo><msub><mrow><mi>I</mi></mrow><mrow><mi>D</mi></mrow></msub></mrow></math></span> method capture design points more efficiently compared to the random sampling of width-to-length (<span><math><mrow><mi>W</mi><mo>/</mo><mi>L</mi></mrow></math></span>) ratios. Furthermore, experimental validation indicates that the pretrained GNN-EQL model achieves superior performance compared to other pretrained models when the parameter range expands across three different amplifier designs. Finally, our approach significantly reduces the required samples by up to 20X when adapting the pretrained model to broader parameter ranges, compared to training a new model from scratch.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102551"},"PeriodicalIF":2.5000,"publicationDate":"2025-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Integration-The Vlsi Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0167926025002081","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
Analog integrated circuit design typically involves extensive analytical derivations to evaluate circuit performance metrics. Although SPICE simulations facilitate efficient prediction of these metrics, the simulation process remains time-consuming as the dimensionality of circuit parameters increases. In this article, we propose integrating Graph Neural Networks (GNN) with Equation Learner Networks (EQL), employing them as pretrained models within a limited range of design parameters. Our results demonstrate that datasets constructed using the method capture design points more efficiently compared to the random sampling of width-to-length () ratios. Furthermore, experimental validation indicates that the pretrained GNN-EQL model achieves superior performance compared to other pretrained models when the parameter range expands across three different amplifier designs. Finally, our approach significantly reduces the required samples by up to 20X when adapting the pretrained model to broader parameter ranges, compared to training a new model from scratch.
期刊介绍:
Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics:
Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.