An X-Band Hybrid Three-Stack Power Amplifier With High Reliability in 65-nm Bulk CMOS

Abstract

We present a hybrid power amplifier (PA) using a three-stacked FET architecture in 65-nm bulk CMOS technology. To handle high voltage swings under a 3.3-V supply, the top stack FET uses a 2.5-V thick-oxide device, while thin-oxide devices are used in the first and second stacks. Properly sized capacitors are incorporated at each gate node to ensure impedance matching and proper voltage distribution. A current-mode combiner at both input and output forms a four-way structure for enhanced output power and efficiency. The fabricated PA achieves a power gain of 23.2 dB, a 3-dB bandwidth of 1 GHz, a peak power-added efficiency (PAE) of 24%, and a saturated output power (Psat) of 20.9 dBm. Under 256-QAM modulation, it delivers an error vector magnitude (EVM) less than −35 dB, an average output power of 12.7 dBm, an average PAE of 4.58%, and an adjacent channel power ratio (ACPR) of −33.5 dBc. Reliability tests confirm that the proposed architecture successfully meets JEDEC standards in both high-temperature operating life (HTOL) and highly accelerated stress test (HAST), thereby demonstrating stable and reliable performance.