A Vernier TDC With a Time Multiplier Achieving FoM of 0.079 pJ/Conversion

Abstract

Compared with conventional time-to-digital converters (TDCs) with a single oscillator, Vernier TDCs enhance time resolution by having two separate oscillators. To achieve a smaller time resolution, either advanced processes or higher frequency can be used at the expense of higher cost or larger power. To overcome this problem, conventional Vernier TDCs have been developed in conjunction with pulse shrinking and time amplifying schemes that acquire additional resolutions from the residue time. However, these methods cause a dead zone and gain nonlinearity for a small residue time. Moreover, jitter degrades gain error in the conventional Vernier TDC while amplifying the residue time. This article proposes a Vernier TDC with a time multiplier (TM) that eliminates dead zone, reduces the effect of jitter, and increases linearity by having multiple residue times. The proposed Vernier TDC in 180-nm CMOS achieves the effective number of bits of 12.38 at 2.66 MS/s while consuming 1.12-mW power. The figure of merit (FoM) of the proposed TDC is 0.079 pJ/conversion, which exhibits at least 2.15 times superior to prior state-of-the-art.