Exploring analog VLSI architectures for linear regulators and high-speed receivers: a comprehensive SLR and emerging innovations

Abstract

This paper thoroughly examines the current research on analog VLSI designs, with an emphasis on linear regulators and high-speed receivers. The main goal is to examine and evaluate design methodologies that increase power supply rejection ratio (PSRR), optimize power consumption, and enhance bandwidth for high-speed receivers. The evaluation also emphasizes new advancements in digital-assisted analog designs and adaptive equalization methods that reduce signal distortion. Experimental findings illustrate the efficacy of the suggested frameworks in enhancing performance across diverse applications in communication and power control systems.