{"title":"Implementation of imprecise multipliers using 2-bit adder for image processing","authors":"Parthibaraj Anguraj , Thiruvenkadam Krishnan","doi":"10.1016/j.vlsi.2025.102510","DOIUrl":null,"url":null,"abstract":"<div><div>The inexact multiplier architecture represents a foundational element of approximate computing, serving a critical function across diverse error-tolerant applications. This paper delves into the complexities of three distinct inexact multiplier designs, each meticulously optimized for image processing applications. This work introduces a strategic partitioning of the partial product stage into smaller segments, subsequently implementing decoder algorithms, truncation methods, exact 2-bit adder and proposed multiplexer-based imprecise 2-bit adder circuits. These resulting 8<span><math><mo>×</mo></math></span> 8 imprecise multipliers exhibit advantageous error metrics and streamlined design complexity. When benchmarked against traditional inexact multipliers, these architectures achieve notable reductions in both area and power consumption, as validated by modeling conducted via the Cadence RTL compiler with TSMC’s 90 nm technology. The proposed approximation model demonstrates substantial area and power reductions of 37.19% and 46.14%, respectively, compared to precise multipliers, all while sustaining acceptable error metrics. Additionally, the developed 8<span><math><mo>×</mo></math></span> 8 multipliers surpass other approximate multiplier architectures in performance metrics, making them particularly effective for image multiplication and sharpening.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102510"},"PeriodicalIF":2.5000,"publicationDate":"2025-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Integration-The Vlsi Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0167926025001671","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
The inexact multiplier architecture represents a foundational element of approximate computing, serving a critical function across diverse error-tolerant applications. This paper delves into the complexities of three distinct inexact multiplier designs, each meticulously optimized for image processing applications. This work introduces a strategic partitioning of the partial product stage into smaller segments, subsequently implementing decoder algorithms, truncation methods, exact 2-bit adder and proposed multiplexer-based imprecise 2-bit adder circuits. These resulting 8 8 imprecise multipliers exhibit advantageous error metrics and streamlined design complexity. When benchmarked against traditional inexact multipliers, these architectures achieve notable reductions in both area and power consumption, as validated by modeling conducted via the Cadence RTL compiler with TSMC’s 90 nm technology. The proposed approximation model demonstrates substantial area and power reductions of 37.19% and 46.14%, respectively, compared to precise multipliers, all while sustaining acceptable error metrics. Additionally, the developed 8 8 multipliers surpass other approximate multiplier architectures in performance metrics, making them particularly effective for image multiplication and sharpening.
期刊介绍:
Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics:
Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.