A 5.56 ppm/°C curvature-compensated CMOS voltage reference using reverse body biasing technique

Abstract

This paper presents a novel CMOS voltage reference featuring a low temperature coefficient (TC) and low power consumption. Based on the traditional low-voltage ZTC voltage reference architecture, a reverse body biasing temperature compensation technique is introduced into the loop. This approach significantly improves the performance of TC while reducing power consumption. The proposed voltage reference is designed and simulated using a $0.18\mu m$ CMOS process. Simulation results confirm that the reference voltage output is 678 mV, with an average temperature coefficient of 5.56 ppm/$°C$ over a temperature range of −40 °C to 100 °C. The PSRR of the proposed voltage reference is 64.82 dB at 100 Hz. It operates with a minimum supply voltage of 1.05 V, and the compensation circuit structure ensures minimal current consumption, leading to a power consumption of only 1.90 $\mu$W, with a silicon area of 0.025 mm${}^2$.