Implementation and Analysis of Enhanced Performance of Elliptic Curve Cryptography Processor Over Prime Field

Abstract

Designing an optimized performance elliptic curve cryptography (ECC) processor capable of rapid point multiplication while saving hardware resources is an essential part of system security. This study introduces the implementation of a field-programmable gate array (FPGA) design of the ECC processor (ECCP), prioritizing speed, compactness, maximum operating frequency, and resultant throughput rate in the prime field of 256-bit. The processor enables efficient point multiplication for 256 bits in the twisted Edwards25519 curve, which is vital for the strength of the Edwards curve digital signature algorithm (EdDSA). Unique architectures of hardware for different modular and group operations in the twisted Edwards curve are proposed in this work. The processor achieves modular multiplication, point addition, and doubling in only 257, 1286, and 518 clock cycles, respectively. For 256-bit keys, a point multiplication takes 0.51 ms, which operates at the highest frequency of 226.7 MHz with a cycle count of 115.2 k and a throughput of 501.9 Kbps. The implementation, executed on the Kintex-7 platform for FPGA implementation in projective coordinates, utilizes 14.7 k slices. This design demonstrates time- and throughput-efficient design by providing fast scalar multiplication while using minimum hardware resources without compromising security. The proposed ECCP on the Edwards curve's performance is improved in such a way that the device uses optimized area, time, frequency, and throughput rate. To generate a key for the ECCP and EdDSA, we simulate various operations like modular arithmetic operations, group operations, and point operations required for correct ECPM implementation on Xilinx ISE and ModelSim. Then we verify these results using the Maple tool.