{"title":"A Novel High-Speed Ultralow Power Double-Node-Upsets Tolerant Automotive Latch Design","authors":"Guoji Qiu, Dawei Bi, Zhiyuan Hu, Zhengxuan Zhang","doi":"10.1002/cta.4401","DOIUrl":null,"url":null,"abstract":"<div>\n \n <p>This paper introduces a novel High-speed Ultralow power Double-Node Upsets (DNU) Tolerant Automotive Latch (HUDTAL) fabricated in the 55-nm CMOS technology. Through the integration of Muller-C-Element (MCE), Node-Hardened MCE, CLK-Gating MCE (CG-MCE), and Transmission Gate techniques, the proposed latch can fully resist DNU. Compared with similar types of latches through simulation, the proposed latch has higher critical charges and does not generate any TFs at the output that may affect the next stage circuit, saving 4.89% area power delay product on average. Additionally, it exhibits lower sensitivity to process voltage temperature variations, enabling stable operation in harsh environmental conditions.</p>\n </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 9","pages":"5498-5506"},"PeriodicalIF":1.6000,"publicationDate":"2024-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Journal of Circuit Theory and Applications","FirstCategoryId":"5","ListUrlMain":"https://onlinelibrary.wiley.com/doi/10.1002/cta.4401","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
This paper introduces a novel High-speed Ultralow power Double-Node Upsets (DNU) Tolerant Automotive Latch (HUDTAL) fabricated in the 55-nm CMOS technology. Through the integration of Muller-C-Element (MCE), Node-Hardened MCE, CLK-Gating MCE (CG-MCE), and Transmission Gate techniques, the proposed latch can fully resist DNU. Compared with similar types of latches through simulation, the proposed latch has higher critical charges and does not generate any TFs at the output that may affect the next stage circuit, saving 4.89% area power delay product on average. Additionally, it exhibits lower sensitivity to process voltage temperature variations, enabling stable operation in harsh environmental conditions.
期刊介绍：
The scope of the Journal comprises all aspects of the theory and design of analog and digital circuits together with the application of the ideas and techniques of circuit theory in other fields of science and engineering. Examples of the areas covered include: Fundamental Circuit Theory together with its mathematical and computational aspects; Circuit modeling of devices; Synthesis and design of filters and active circuits; Neural networks; Nonlinear and chaotic circuits; Signal processing and VLSI; Distributed, switched and digital circuits; Power electronics; Solid state devices. Contributions to CAD and simulation are welcome.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
