A 1.2–6.6 GHz Sub-sampling PLL with adaptive pulse width match achieving 216 fs rms jitter and − 71.90 dBc reference spurs

Abstract

With the demands for different rates of serial data received and transmitted in a communication system, an adaptive bandwidth sub-sampling phase-locked loop (AB-SSPLL) was designed. To maintain the bandwidth of the AB-SSPLL varying with the reference clock frequency, a self-biasing adaptive pulse width matching technique was introduced to the proposed AB-SSPLL. It adaptively adjusts the gain of the sub-sampling charge pump to maintain a constant ratio of the loop bandwidth to the reference clock frequency. The proposed AB-SSPLL has the advantages of broad bandwidth and low jitter. The AB-SSPLL is designed using a 40 nm COMS process and has an area of 0.21 × 0.26 mm². The simulation results show that the phase-locked loop tuning range is 1.2–6.6 GHz, the root mean square jitter of the output clock is 312.3 fs@1.2 GHz and 216.3 fs@6.6 GHz, and the reference spurious is -71.90 dBc@1.2 GHz and − 61.39 dBc@6.6 GHz, respectively, and the jitter performance of ring-VCO-based AB-SSPLL can be comparable to that of the LC-VCO-based PLL.