Tianci Miao , Qihang Zheng , Yangyang Hu , Xiaoyu Cheng , Jie Liang , Liang Chen , Aiying Guo , Jingjing Liu , Kailin Ren , Jianhua Zhang
{"title":"A novel thermal network model and electro-thermal coupling study for NSFETs and CFETs considering thermal crosstalk","authors":"Tianci Miao , Qihang Zheng , Yangyang Hu , Xiaoyu Cheng , Jie Liang , Liang Chen , Aiying Guo , Jingjing Liu , Kailin Ren , Jianhua Zhang","doi":"10.1016/j.micrna.2025.208322","DOIUrl":null,"url":null,"abstract":"<div><div>As the process node of logic integrated circuits continues to shrink to chase the Moore's Law, nanosheet field effect transistors (NSFETs) and complementary FETs (CFETs) become candidates for the 3 nm and sub-nanometre nodes. However, due to the shrinking device size, self-heating and inter-device thermal crosstalk of NSFETs and CFETs become more severe, leading to degradation of on-state current, threshold voltage shift, and reduced reliability. It is of great significance to accurately calculate the self-heating and thermal crosstalk of devices and to investigate their influences on the electrical and thermal characteristics of logic gates. In this work, a novel thermal network model considering the thermal crosstalk of neighboring devices is proposed, which can accurately calculate the self-heating and thermal crosstalk by introducing a dummy network. The electrical and thermal characteristics of NSFETs and CFETs are compared, and it is found that CFETs suffer more severe self-heating and thermal crosstalk. The electro-thermal characteristics of inverters, logic gates and ring oscillators composed of NSFETs and CFETs are further investigated. Compared with NSFETs, logic gates and ring oscillators composed of CFETs are more seriously affected by self-heating and should be given extra attention. The thermal network model proposed in this work can be further used to study the thermal optimization strategy of devices and circuits to enhance the electrical performances, achieving the design technology co-optimizations (DTCO).</div></div>","PeriodicalId":100923,"journal":{"name":"Micro and Nanostructures","volume":"208 ","pages":"Article 208322"},"PeriodicalIF":3.0000,"publicationDate":"2025-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Micro and Nanostructures","FirstCategoryId":"1085","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S2773012325002511","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"PHYSICS, CONDENSED MATTER","Score":null,"Total":0}
引用次数: 0
Abstract
As the process node of logic integrated circuits continues to shrink to chase the Moore's Law, nanosheet field effect transistors (NSFETs) and complementary FETs (CFETs) become candidates for the 3 nm and sub-nanometre nodes. However, due to the shrinking device size, self-heating and inter-device thermal crosstalk of NSFETs and CFETs become more severe, leading to degradation of on-state current, threshold voltage shift, and reduced reliability. It is of great significance to accurately calculate the self-heating and thermal crosstalk of devices and to investigate their influences on the electrical and thermal characteristics of logic gates. In this work, a novel thermal network model considering the thermal crosstalk of neighboring devices is proposed, which can accurately calculate the self-heating and thermal crosstalk by introducing a dummy network. The electrical and thermal characteristics of NSFETs and CFETs are compared, and it is found that CFETs suffer more severe self-heating and thermal crosstalk. The electro-thermal characteristics of inverters, logic gates and ring oscillators composed of NSFETs and CFETs are further investigated. Compared with NSFETs, logic gates and ring oscillators composed of CFETs are more seriously affected by self-heating and should be given extra attention. The thermal network model proposed in this work can be further used to study the thermal optimization strategy of devices and circuits to enhance the electrical performances, achieving the design technology co-optimizations (DTCO).