{"title":"65.35 nW three-stage charge pump circuit based on swapped body biasing approach","authors":"Ricky Rajora, Kulbhushan Sharma","doi":"10.1007/s10470-025-02483-0","DOIUrl":null,"url":null,"abstract":"<div><p>The recent developments in sustainable energy solutions demand ultra-low power operation of cascaded charge pump (CP) circuits. This work reports a three-stage CP circuit designed using a swapped body biasing (SBB) approach in FinFET (18 nm) technology which showcases notable peak power conversion efficiency of 38.04%, voltage at output of 455.11 mV, power consumption of 65.35 nW, ripple voltage of 19.80 mV and settling time of 80.05 µs (@ 2% band) with input supply voltage of 100 mV. Further, the performance of the designed three-stage CP is investigated for rigorous temperature, process and load variations. The performance of the proposed three-stage CP is better than earlier reported FinFET-based multiple-stage CP designs.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"125 1","pages":""},"PeriodicalIF":1.4000,"publicationDate":"2025-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Analog Integrated Circuits and Signal Processing","FirstCategoryId":"5","ListUrlMain":"https://link.springer.com/article/10.1007/s10470-025-02483-0","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
The recent developments in sustainable energy solutions demand ultra-low power operation of cascaded charge pump (CP) circuits. This work reports a three-stage CP circuit designed using a swapped body biasing (SBB) approach in FinFET (18 nm) technology which showcases notable peak power conversion efficiency of 38.04%, voltage at output of 455.11 mV, power consumption of 65.35 nW, ripple voltage of 19.80 mV and settling time of 80.05 µs (@ 2% band) with input supply voltage of 100 mV. Further, the performance of the designed three-stage CP is investigated for rigorous temperature, process and load variations. The performance of the proposed three-stage CP is better than earlier reported FinFET-based multiple-stage CP designs.
期刊介绍：
Analog Integrated Circuits and Signal Processing is an archival peer reviewed journal dedicated to the design and application of analog, radio frequency (RF), and mixed signal integrated circuits (ICs) as well as signal processing circuits and systems. It features both new research results and tutorial views and reflects the large volume of cutting-edge research activity in the worldwide field today.
A partial list of topics includes analog and mixed signal interface circuits and systems; analog and RFIC design; data converters; active-RC, switched-capacitor, and continuous-time integrated filters; mixed analog/digital VLSI systems; wireless radio transceivers; clock and data recovery circuits; and high speed optoelectronic circuits and systems.
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