Hop-CIM: An all-digital two-level approximate SRAM-CIM macro for high energy-efficient HNN acceleration with data-aware early exit and column-wise partial-sum reuse

Abstract

Hopfield Neural Networks (HNNs) have emerged as a promising paradigm for image restoration tasks with the inner associative memory properties to corrupted image reconstruction. However, traditional HNN accelerators relying on full-precision vector-matrix multiplication (VMM) operations introduce significant computational redundancy, as the binary state updates process of HNNs depend solely on the sign of VMM results rather than their precise values. To address this inefficiency, Hop-CIM, an all-digital approximate SRAM-based computing-in-memory (SRAM-CIM) macro, is proposed for energy-efficient HNN acceleration. The key innovation points of the proposed Hop-CIM include: (1) a two-level approximation strategy that fully exploits the error-tolerant characteristics of HNNs, (2) a data-aware threshold-based early exit mechanism during tile-by-tile partial-sum accumulation, and (3) a partial-sum reuse method with column-wise weight matrix compression. The combined effect of (2) and (3) reduces the redundant multiply-and-accumulate (MAC) operations by 55.7 %. Experimental results demonstrate that under 28 nm technology node, the proposed Hop-CIM macro delivers 1591TOPS/W energy efficiency with 1-bit/1-bit input/weight quantization, outperforming the traditional full-precision SRAM-CIM design with 1-bit/3-bit input/weight quantization and the approximate SRAM-CIM design with 1-bit/1-bit input/weight quantization by 7.72x and 2.48x, respectively. In addition, Hop-CIM achieves 0.944 in structural similarity index measure (SSIM) for 28 × 28 image restoration.