SCCS: A neuromorphic architecture supporting synapse compression for converted spiking neural networks

Abstract

Neuromorphic computing emulates the information processing of the biological brain, providing a potential solution to the memory and power consumption limitations of the traditional von Neumann architecture. However, due to immature spiking neural network (SNN) learning algorithms, many high-performance SNN applications are converted from artificial neural networks (ANNs). Existing neuromorphic hardware faces challenges in deploying converted SNNs due to limited synaptic storage and spatiotemporal traffic imbalances. Therefore, this paper proposes a novel neuromorphic architecture supporting synapse compression for converted SNNs, namely SCCS. A storage-free synaptic addressing technique minimizes the memory used for synaptic. Additionally, a multicast-supported hybrid hierarchical architecture was adopted for load balance communication. To evaluate SCCS, we developed a prototype design and synthesized it using the SMIC 55-nm low-power process. The prototype accommodates approximately 589K neurons and 130M synapses, occupying only 16 $m{m}^2$ of area. The neuron and synapse density of our design remains advantageous compared to the state-of-the-art neuromorphic hardware fabricated with a 4-nm process. Our design achieves a maximum throughput of 9.6 billion spikes per second per cluster, which is nearly three times higher than similar research. Finally, we constructed an FPGA verification platform to assess performance using real-world applications.