Extending low-temperature sintering technique to large-sized whole-wafer power semi-conductor devices

Abstract

With the enormous growth in the capacity of electrical equipment, power semi-conductor devices are developing rapidly towards larger size and higher capacity. To suppress the thermal resistance and achieve efficient heat dissipation, the authors focus on developing a low-temperature sintering technique for wafer-level high-power semi-conductor devices. In detail, a 6-inch whole-wafer device was successfully fabricated by sintering the Si chip and Mo plate using a pulsed laser deposition (PLD)-based nano-Ag layer at a sintering temperature of 250°C, revealing edgewise delamination on the sintered layer. The formation mechanism of the destructive delamination was then unveiled, identifying excessive residual thermal stress due to an inappropriate sintering temperature as the ringleader. Furthermore, an optimisation methodology of the sintering temperature for the PLD-based nano-Ag layer was proposed, determining an optimal temperature range spanning from 190 to 211°C. Finally, a 6-inch sintered chip, the largest to date, was successfully fabricated with adequate integrity, robust reliability, and excellent thermal and electrical performance, evidentially verifying the feasibility of the nano-Ag-based sintering technique on large-sized whole-wafer semi-conductor devices.