BTI Aging Analysis and Mitigation for Differential Input In-Memory Computing SRAMs

Abstract

SRAM-based in-memory computing (IMC) is a promising approach to overcome the bottleneck of traditional Von Neumann architectures that suffer from data transfer delay and energy inefficiency. Aging phenomena and process variations are a serious reliability and lifetime concern that may impact SRAM-based IMC array architectures, similar to conventional SRAM arrays. Bias temperature instability (BTI) is a dominant aging mechanism that degrades transistor performance and negatively affects the analog nature of the IMC computations. In this work, we present a simulation framework for the joined analysis of aging and process variation influence on IMC reliable operation. We perform, through SPICE simulations, an extensive BTI aging analysis on differential input SRAM-based IMC array architectures under different operating conditions and considering process variations. The simulation results show a substantial impact of aging on their reliability. Furthermore, we present an aging mitigation technique to maintain reliability and extend the lifetime of these circuits. Aging mitigation is achieved by periodically reconfiguring the active current paths in the IMC cells, with negligible cost on throughput and power consumption. The simulation results show that up to 68% of the IMC circuits can lose accuracy after three operating years, depending on the operating conditions. The aging mitigation technique effectively reduces the percentage of circuits that lose accuracy by up to 72% and decreases their degradation rate, essentially extending by more than $9.3\times $ their reliable lifetime.