Implementation of two new 10-bit 1 GS/s hybrid DACs with a novel gain error calibration technique

Abstract

This paper presents two novel low-power 10-bit hybrid digital-to-analog converters (DACs): ground-connected-ladder DAC (GCL-DAC) and Vdd-connected-ladder DAC (VCL-DAC). The proposed hybrid DACs benefit from a combination of differential resistor ladders and current sources. By utilizing this combination, the number of unit current cells and the complexity of decoders are considerably reduced. Moreover, the proposed hybrid DACs consist of 21 unit current cells and a 6-bit differential resistor ladder, significantly reducing the area and power consumption. A background calibration method is also used to correct the gain error and provide a full swing in the output of both hybrid DACs. The static and dynamic performance of the two proposed DACs is also compared. The proposed DACs are post-layout simulated in 65 nm CMOS technology. The GCL-DAC and VCL-DAC consume 10.98 mW and 9.71 mW of power with a 1.2 V supply voltage. The static specifications of the Integral-Non-Linearity (INL) and Differential-Non-Linearity (DNL) for both DACs are below 0.9 LSB and 0.4 LSB, respectively. Furthermore, the occupation area for GCL-DAC and VCL-DAC is 0.021 mm² and 0.026 mm², respectively. Moreover, both structures are robust against process variations and work properly at the temperature ranges of −40 to 80 °C.