Area-efficient architectures of Midori lightweight block cipher for resource constrained devices

Abstract

The practise of tiny computing and embedded devices in Internet of Things (IoT) has brought up severe security trepidations in information security. Providing secured end-to-end communication in Resource Constrained Environment (RCE) with limited hardware is challenging task. Over the past few year, Lightweight Cryptography has been recognized as top-notch for gratifying the requirements of RCE. Several lightweight cryptographic algorithms have been proposed for different applications in RCEs. In this paper, Midori block cipher has been chosen to fulfil the objective. Midori block cipher has been area and speed optimized using unconventional serial architectures and memory address scheduling technique. This paper presents two serial architectures M1 and M2 for 64 and 128-bit block size respectively. The proposed designs are implemented in verilog Hardware Descriptive Language (HDL) using Xilinx Integrated Synthesis Environment (ISE) Design suite and power analysis has been done. The hardware implementation is carried on Field Programmable Gate Array (FPGA). Comparison of the proposed designs has been done on different families of FPGA. The proposed designs has shown a percentage improvement of 38.54% and 36.12% in terms of area for 64 and 128-bit block size respectively. Similarly, the percentage improvement for efficiency is 80.18% and 210.41%, for throughput is 10.69% and 98.13% for 64 and 128-bit block size respectively on FPGA Spartan 6 platform comparing with state-of-the-art Midori cipher.