Hardware Trojan Design With Low Overhead and High Destructiveness for STT-MRAM-Based CIMs

Abstract

To overcome the von Neumann bottleneck, computing-in-memories (CIMs) have emerged as a design trend. On the other hand, with the globalization of the semiconductor supply chain, hardware Trojans have become a significant security concern. While there have been some studies on hardware Trojan designs for embedded memories in the past, there is no literature addressing hardware Trojan designs for CIMs. In this article, we propose a hardware Trojan design for spin transfer torque magnetoresistive random access memory (STT-MRAM)-based CIMs that can disrupt computing-mode operations. Our trigger circuit can evade detection during post-manufacturing memory testing, and our payload circuit can disrupt over 99% of CIM operations. Experimental results also demonstrate that compared to the original peripheral circuits of STT-MRAM-based CIMs, the area overhead and power overhead (at the TT process corner) caused by our inserted hardware Trojan are only 1.023% and 0.123%, respectively. Therefore, our hardware Trojan can easily hide within the peripheral circuits.