Asymmetric and Adaptive Error Correction in STT-MRAM

Abstract

Spin-transfer torque magnetic random access memory (STT-MRAM) has emerged as a promising alternative to conventional CMOS memory technologies for on-chip cache replacement. Due to its superior access speeds, high endurance, and scalability, it is being extensively considered a promising candidate for last-level cache replacement. This technology has reached considerable industrial maturity, with several foundries now offering this emerging technology. Despite its advantages, STT-MRAM faces reliability challenges, primarily due to its asymmetric error characteristics during write and read operations, where the likelihood of a bit transitioning from $1\rightarrow 0$ differs from that of $0\rightarrow 1$ . Conventional Error Correcting Codes (ECCs) do not account for such asymmetry between these bit-flip types and fall short of providing balanced error correction. This article introduces an efficient asymmetric and adaptive error correction in STT-MRAM based on the Hamming weight of data bits that operates with negligible overhead alongside a standard ECC framework. Our simulation findings indicate that the proposed technique offers substantial enhancement in reliability, measured by a cache word/block error rate, tested across the last level cache data for various SPEC CPU2017 benchmarks. This enhancement in reliability is achieved without inserting excessive memory and hardware overhead, and without impacting system performance, presenting a compelling case for enhancing the operational reliability of STT-MRAM.