SIRENA: SparsIty-REpetition aware Nibble-based hardware Accelerator for convolutional neural networks

IF 4.1 2区计算机科学 Q1 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Journal of Systems Architecture Pub Date : 2025-08-11 DOI:10.1016/j.sysarc.2025.103529

Laura Medina, Jose Flich

引用次数: 0

Abstract

The growing demand for artificial intelligence (AI) applications demands specialized hardware accelerators to handle intensive computational loads. To reduce computing needs, this paper introduces nibble decomposition (NBD), a method that splits 8-bit values into two 4-bit nibbles to detect and remove redundant computations in convolutional neural networks (CNNs). Experiments with INT8 quantized ResNet-50, MobileNet, and YOLO-V3 show that nibble decomposition can avoid up to 91% of multiplications in the upper nibble and 70% in the lower nibble.

We further propose SIRENA, an NBD hardware accelerator to optimize 8-bit quantized CNNs by skipping redundant operations without accuracy loss. Building on this method, we present SIRENA, an NBD-based accelerator that skips redundant operations without accuracy loss. Compared to a conventional value-agnostic accelerator, SIRENA achieves a 55% reduction in power consumption.

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SIRENA：用于卷积神经网络的基于nibble的稀疏重复感知硬件加速器

对人工智能（AI）应用日益增长的需求需要专门的硬件加速器来处理密集的计算负载。为了减少计算需求，本文引入了nibble decomposition (NBD)，一种将8位值分成两个4位的nibble来检测和去除卷积神经网络（cnn）中的冗余计算的方法。使用INT8量化的ResNet-50、MobileNet和YOLO-V3进行的实验表明，啃食分解可以避免高达91%的上啃食乘法和70%的下啃食乘法。我们进一步提出了NBD硬件加速器SIRENA，通过跳过冗余运算而不损失精度来优化8位量化cnn。在此方法的基础上，我们提出了SIRENA，一种基于nbd的加速器，可以跳过冗余操作而不损失精度。与传统的不确定值的加速器相比，SIRENA的功耗降低了55%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Journal of Systems Architecture 工程技术-计算机：硬件

CiteScore

8.70

自引率

15.60%

发文量

226

审稿时长

46 days

期刊介绍： The Journal of Systems Architecture: Embedded Software Design (JSA) is a journal covering all design and architectural aspects related to embedded systems and software. It ranges from the microarchitecture level via the system software level up to the application-specific architecture level. Aspects such as real-time systems, operating systems, FPGA programming, programming languages, communications (limited to analysis and the software stack), mobile systems, parallel and distributed architectures as well as additional subjects in the computer and system architecture area will fall within the scope of this journal. Technology will not be a main focus, but its use and relevance to particular designs will be. Case studies are welcome but must contribute more than just a design for a particular piece of software. Design automation of such systems including methodologies, techniques and tools for their design as well as novel designs of software components fall within the scope of this journal. Novel applications that use embedded systems are also central in this journal. While hardware is not a part of this journal hardware/software co-design methods that consider interplay between software and hardware components with and emphasis on software are also relevant here.