A novel SiC super-junction MOSFET with step-doping profile and split dummy gate for enhanced switching and short-circuit performance

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal Pub Date : 2025-08-14 DOI:10.1016/j.mejo.2025.106837

Lixin Geng, Ruifeng Yue, Yan Wang

{"title":"A novel SiC super-junction MOSFET with step-doping profile and split dummy gate for enhanced switching and short-circuit performance","authors":"Lixin Geng, Ruifeng Yue, Yan Wang","doi":"10.1016/j.mejo.2025.106837","DOIUrl":null,"url":null,"abstract":"<div><div>A 4H-SiC super-junction (SJ) MOSFET with the step-doping profile and split dummy gate (SDG-SD-SJ) is proposed in this work. To further improve the static performance based on the conventional SiC SJ MOSFET (Con-SJ), the conventional P-N pillars are replaced by a step-doping profile in the drift region. The static figure of merit (FOM) (BV<sup>2</sup>/<em>R</em><sub>on, sp</sub>) of the proposed device is about 2.5 and 1.6 times the conventional SiC MOSFET (Con-MOS) and Con-SJ, respectively. This is due to the increased average doping concentration of the conductive n-type pillar and the reduced electric field peak. Moreover, the dynamic FOM (<em>R</em><sub>on, sp</sub> × <em>Q</em><sub>GD</sub>) of the SDG-SD-SJ is reduced by 85 % compared to the SiC SJ MOSFET with a step-doping profile (SD-SJ). This is mainly attributed to the introduction of the split dummy gate structure in the proposed device. Furthermore, the significantly enhanced switching and short-circuit performance further demonstrates the great potential of the proposed SDG-SD-SJ in the field of power-switching applications.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"165 ","pages":"Article 106837"},"PeriodicalIF":1.9000,"publicationDate":"2025-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S1879239125002863","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}

引用次数: 0

Abstract

A 4H-SiC super-junction (SJ) MOSFET with the step-doping profile and split dummy gate (SDG-SD-SJ) is proposed in this work. To further improve the static performance based on the conventional SiC SJ MOSFET (Con-SJ), the conventional P-N pillars are replaced by a step-doping profile in the drift region. The static figure of merit (FOM) (BV²/R_{on, sp}) of the proposed device is about 2.5 and 1.6 times the conventional SiC MOSFET (Con-MOS) and Con-SJ, respectively. This is due to the increased average doping concentration of the conductive n-type pillar and the reduced electric field peak. Moreover, the dynamic FOM (R_{on, sp} × Q_GD) of the SDG-SD-SJ is reduced by 85 % compared to the SiC SJ MOSFET with a step-doping profile (SD-SJ). This is mainly attributed to the introduction of the split dummy gate structure in the proposed device. Furthermore, the significantly enhanced switching and short-circuit performance further demonstrates the great potential of the proposed SDG-SD-SJ in the field of power-switching applications.

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一种新型的SiC超结MOSFET，具有阶跃掺杂和分裂假门，可增强开关和短路性能

本文提出了一种具有步进掺杂和分裂假栅的4H-SiC超结MOSFET （SDG-SD-SJ）。为了进一步提高基于传统SiC SJ MOSFET （Con-SJ）的静态性能，在漂移区采用阶梯掺杂的方式取代了传统的P-N柱。该器件的静态性能系数（FOM）（BV2/Ron, sp）分别是传统SiC MOSFET （Con-MOS）和Con-SJ的2.5倍和1.6倍。这是由于导电n型柱的平均掺杂浓度增加，电场峰降低。此外，与阶跃掺杂的SiC SJ MOSFET （SD-SJ）相比，SDG-SD-SJ的动态FOM （Ron, sp × QGD）降低了85%。这主要是由于在提出的装置中引入了分裂假门结构。此外，显著增强的开关和短路性能进一步证明了所提出的SDG-SD-SJ在功率开关应用领域的巨大潜力。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Microelectronics Journal 工程技术-工程：电子与电气

CiteScore

4.00

自引率

27.30%

发文量

222

审稿时长

43 days

期刊介绍： Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.