Temperature-aware optimal repeater insertion for multilayer graphene nanoribbon interconnects

Abstract

In this paper, a temperature-aware power-delay product (PDP) optimization model for repeater insertion in multilayer graphene nanoribbon (MLGNR) interconnects for different technology nodes is presented. The model is solved using the sparrow search algorithm (SSA) to determine the optimal number and size of repeaters for MLGNR interconnects. For comparative analysis, the same optimization procedure is also applied to copper (Cu) interconnects. At room temperature, the optimal repeater metrics including optimal number of repeaters, optimal repeater size, and figure of merit (FoM), are compared between MLGNR and Cu interconnects. It is found that MLGNR interconnects significantly outperform their Cu counterparts, requiring fewer optimal repeaters, smaller optimal repeater size, and yielding a better FoM. In addition, the impact of temperature variation on repeater optimization metrics is investigated for both MLGNR and Cu interconnects. It is demonstrated that elevated temperatures lead to an increase in the optimal number of repeaters up to 23.6 % for Cu and 9.0 % for MLGNR, while the optimal repeater size tends to decrease. The FoM for repeater optimization increases with temperature, showing maximum gains of 23.9 % for Cu and 10.4 % for MLGNR. Also, the effects of electronic Fermi level, edge roughness, contact resistance, and intrinsic parameters (i.e., driver resistance, driver capacitance, and load capacitance) of the minimum-sized gate on repeater optimization metrics are thoroughly examined. Simulation results indicate that enhancing the Fermi level, reducing edge roughness, minimizing contact resistance, and reducing intrinsic parameters of the minimum-sized gate can decrease the FoM and enhance the performance for repeater optimization in MLGNR interconnects.