A 14-bit 2-MS/s pure-window SAR ADC with dual-threshold comparator

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal Pub Date : 2025-08-13 DOI:10.1016/j.mejo.2025.106844

Sha Li , Qiao Meng , Lizhen Zhang , Jie Wu

{"title":"A 14-bit 2-MS/s pure-window SAR ADC with dual-threshold comparator","authors":"Sha Li , Qiao Meng , Lizhen Zhang , Jie Wu","doi":"10.1016/j.mejo.2025.106844","DOIUrl":null,"url":null,"abstract":"<div><div>- A 14-bit 2-MS/s pure-window (PW) successive approximation register (SAR) analog-to-digital converter (ADC) based on dual-threshold comparator is presented. As the dual-threshold comparator inherently provides switching window, a novel PW switching technique is introduced and implemented to all conversion cycles, featuring low power consumption and variable windows. The proposed PW redundancy technique highlights no additional redundant capacitors and conversion cycles. As long as the condition of dual-threshold voltages is met, PW redundancy not only enhances the conversion speed, but also realizes nearly 1-bit improvement in resolution. Four dual-threshold voltages are realized by the multi-stage dual-threshold comparator with a straightforward structure. The prototype ADC is implemented in a 180 nm CMOS technology with an effective area of 1.16 mm<sup>2</sup>, achieving the signal-to-noise-and-distortion ratio (SNDR) of 83.90 dB and spurious-free dynamic range (SFDR) of 97.85 dB at a Nyquist input. The peak differential nonlinearity (DNL) and integral nonlinearity (INL) are −0.86/+0.66LSB and −0.73/+1.60LSB, respectively.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"165 ","pages":"Article 106844"},"PeriodicalIF":1.9000,"publicationDate":"2025-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S1879239125002930","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}

引用次数: 0

Abstract

- A 14-bit 2-MS/s pure-window (PW) successive approximation register (SAR) analog-to-digital converter (ADC) based on dual-threshold comparator is presented. As the dual-threshold comparator inherently provides switching window, a novel PW switching technique is introduced and implemented to all conversion cycles, featuring low power consumption and variable windows. The proposed PW redundancy technique highlights no additional redundant capacitors and conversion cycles. As long as the condition of dual-threshold voltages is met, PW redundancy not only enhances the conversion speed, but also realizes nearly 1-bit improvement in resolution. Four dual-threshold voltages are realized by the multi-stage dual-threshold comparator with a straightforward structure. The prototype ADC is implemented in a 180 nm CMOS technology with an effective area of 1.16 mm², achieving the signal-to-noise-and-distortion ratio (SNDR) of 83.90 dB and spurious-free dynamic range (SFDR) of 97.85 dB at a Nyquist input. The peak differential nonlinearity (DNL) and integral nonlinearity (INL) are −0.86/+0.66LSB and −0.73/+1.60LSB, respectively.

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带双阈值比较器的14位2 ms /s纯窗口SAR ADC

提出了一种基于双阈值比较器的14位2 ms /s纯窗（PW）逐次逼近寄存器（SAR）模数转换器（ADC）。由于双阈值比较器固有的开关窗口，引入了一种新颖的PW开关技术，并实现了所有转换周期，具有低功耗和可变窗口。提出的PW冗余技术强调没有额外的冗余电容器和转换周期。只要满足双阈值电压条件，PW冗余不仅提高了转换速度，而且分辨率提高了近1位。采用结构简单的多级双阈值比较器实现了4个双阈值电压。该原型ADC采用180nm CMOS技术，有效面积为1.16 mm2，在Nyquist输入下实现了83.90 dB的信噪比和97.85 dB的无杂散动态范围。峰值微分非线性（DNL）和积分非线性（INL）分别为- 0.86/+0.66LSB和- 0.73/+1.60LSB。

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来源期刊

Microelectronics Journal 工程技术-工程：电子与电气

CiteScore

4.00

自引率

27.30%

发文量

222

审稿时长

43 days

期刊介绍： Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.