A 78.1 dB SNDR 10 MHz-BW continuous-time noise-shaping SAR ADC in 28 nm CMOS

Abstract

A two-step analog-to-digital (ADC) structure that hybridizes continuous-time (CT) and noise-shaping (NS) successive-approximation-register (SAR) ADC can achieve high-speed while maintaining easy driving, anti-aliasing and high energy efficiency. However, the noise leakage caused by the RC time-constant mismatch and gain error of the inter-stage filter significantly limits the revolution and robustness. This work proposes a third-order mismatch and error shaping (MES) technique to address the issue without foreground/background calibration. Furthermore, to reduce the additional amplitude that increased cause by high-frequency input signals, a Gm-C filter with pre-subtraction (PS) technique was proposed. Designed in 28-nm CMOS, the prototype demonstrates a peak SNDR of 78.1 dB within a 10-MHz bandwidth, operating at 320 MS/s with a power consumption 2.6 mW. This results in a Schreier figure of merit (FoMs) of 173.9 dB. Additionally, the SNDR remains above 72 dB across RC time-constant mismatch and/or gain error ranging from −20 % to +20 %.