Single-event burnout hardening in p-GaN HEMTs: An embedded polarization-modulated composite barrier layer approach

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal Pub Date : 2025-08-11 DOI:10.1016/j.mejo.2025.106842

Xingyu Luo , Yanjun Wu , Yang Zuo , Sheng Gao

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Abstract

This paper presents a radiation-hardened p-GaN high electron mobility transistor with an embedded polarization-modulated barrier layer (PMB-HEMT) featuring graded Al composition. The design redistributes the peak electric field from the gate edge to the drain side of the polarization layer, extending the depletion region and stabilizing drain voltage distribution. Additionally, holes generated by the polarization layer effectively neutralize electron accumulation during heavy ion strikes, suppressing carrier buildup and reducing impact ionization near the gate and drain. This innovation significantly enhances the device's radiation tolerance while maintaining robust electrical performance. Simulation results demonstrate that, with a polarization modulation layer length (L) of 4 μm and a thickness (T) of 20 nm, the PMB-HEMT attains a single-event burnout voltage (V_seb) of 1160 V, compared to 290 V for the conventional HEMT (C-HEMT), representing an impressive 300 % enhancement. Additionally, the breakdown voltage (BV) increases from 696 V to 1448 V, marking a 108 % improvement, while the saturation current (I_D) rises by 32.7 %.

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p-GaN hemt的单事件燃烬硬化：一种嵌入式极化调制复合势垒层方法

本文提出了一种具有梯度Al成分的嵌入式极化调制势垒层（PMB-HEMT）的辐射硬化p-GaN高电子迁移率晶体管。该设计将峰值电场从栅极边缘重新分布到极化层的漏极侧，扩大了耗尽区，稳定了漏极电压分布。此外，极化层产生的空穴有效地中和了重离子撞击过程中的电子积累，抑制了载流子的积累，减少了栅极和漏极附近的冲击电离。这一创新显著提高了器件的辐射耐受性，同时保持了稳健的电气性能。仿真结果表明，当偏振调制层长度(L)为4 μm，厚度(T)为20 nm时，PMB-HEMT的单事件燃烬电压（Vseb）为1160 V，相比于传统HEMT （C-HEMT）的290 V，提高了300%。此外，击穿电压（BV）从696 V增加到1448 V，提高了108%，而饱和电流（ID）增加了32.7%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Microelectronics Journal 工程技术-工程：电子与电气

CiteScore

4.00

自引率

27.30%

发文量

222

审稿时长

43 days

期刊介绍： Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.