A double auxiliary gate SiC trench MOSFET with dynamic P-well control and integrated MOS-channel diode

IF 1.9 3区 工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC
Weizhong Chen , Zesheng Chen , Zhijie Deng , Yufan Xiao , Haishi Wang
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引用次数: 0

Abstract

An asymmetric trench SiC MOSFET featuring Double Auxiliary Gate (DAG-ATMOS) is proposed to enhance both forward conduction and reverse recovery performance. The Auxiliary Gate (AG) is inserted beside the Auxiliary Source (AS) in the P-well, and a P-type barrier region (P-re) controlled by AG is formed between AG and AS. During the on-state, AG and AS jointly completely deplete the P-re under a gate-to-source voltage (VGS) of 15 V, disconnecting the P-well from the source and leaving it floating. This reduces the JFET region resistance (RJFET). At the reverse conduction, AS introduces a low-barrier MOS-channel diode with a lower reverse conduction threshold voltage (Vcut-in) compared with the body diode, effectively eliminating the bipolar degradation by suppressing the conduction of parasitic body diode. Simulation results show that the DAG-ATMOS demonstrates a specific on-resistance (Ron,sp) of 2.64 mΩ cm2 and RJFET of 0.94 mΩ cm2, representing reductions of 7.2 % and 16.8 %, respectively, compared to conventional ATMOS. The Vcut-in of the DAG-ATMOS is 2.0 V, 0.8 V lower than the conventional structure, while the reverse recovery charge (QRR) is reduced by 79.2 %.
具有动态p阱控制和集成mos沟道二极管的双辅助栅SiC沟道MOSFET
提出了一种具有双辅助栅极的非对称沟槽SiC MOSFET (DAG-ATMOS),以提高正向导通和反向恢复性能。辅助栅极(AG)插在p阱的辅助源(AS)旁边,在AG与AS之间形成一个由AG控制的p型势垒区(P-re)。在导通状态期间,AG和AS在15 V的栅源电压(VGS)下共同完全耗尽P-re,将p阱与源断开并使其浮动。这降低了JFET区域电阻(RJFET)。在反导处,AS引入了一个低势垒mos通道二极管,其反导阈值电压(Vcut-in)比本体二极管低,通过抑制寄生本体二极管的导通,有效消除了双极退化。仿真结果表明,DAG-ATMOS的导通电阻(Ron,sp)为2.64 mΩ cm2, RJFET为0.94 mΩ cm2,与传统ATMOS相比分别降低了7.2%和16.8%。DAG-ATMOS的电压cut-in为2.0 V,比传统结构低0.8 V,而反向回收电荷(QRR)降低了79.2%。
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来源期刊
Microelectronics Journal
Microelectronics Journal 工程技术-工程:电子与电气
CiteScore
4.00
自引率
27.30%
发文量
222
审稿时长
43 days
期刊介绍: Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.
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