A Fractional Spur Cancellation Technique for Fractional-N Frequency Synthesizers Enabled by Dual Loop Phase Clamping

Abstract

This paper proposes a fractional spur cancellation technique designed for fractional-N frequency synthesizers. A time domain quantitative analysis is conducted to provide an intuitive understanding of the origin of fractional spurs and to formulate the relationship between the phase error of the feedback signal and the division factor of the frequency divider. By utilizing a dual loop charge-pump based architecture that generates two feedback phases, one leading and one lagging the reference phase, the two loops effectively clamp the reference phase between the two feedback phases and inject complementary charge components to achieve spur reduction. Unlike conventional methods, the proposed analog spur cancellation technique eliminates the need for additional signal processing stages within the loop. This offers several advantages, including reduced complexity, no introduction of additional distortion sources, and minimal impact on loop dynamics. Simulation results employing TSMC 40nm technology demonstrate that the proposed technique can achieve a worst-case fractional spur level of -96.6dBc in a charge-pump based fractional-N frequency synthesizer, offering moderate immunity to mismatches while also slightly improving the phase acquisition time and jitter performance.