Optimization of DTC-Based and Harmonic-Mixer-Based Fractional-N PLLs: Comparative Analysis of Jitter and Power Trade-Offs

Abstract

As phase-locked loop (PLL) architectures become increasingly complex, optimizing the jitter and power performance through calculation alone is becoming more challenging for fractional-N PLLs. To find the most suitable PLL architecture that meets the jitter-power requirements of various applications, a simple and widely-applicable method is in demand to find the optimal jitter-power relation of different PLL architectures. In this paper, we propose the use of a multi-objective evolutionary algorithm (MOEA) to optimize the jitter and power of PLLs, specifically focusing on two popular fractional-N PLL architectures: digital-to-time converter (DTC)-based and harmonic-mixer (HM)-based PLLs. By applying the MOEA, we can achieve optimal jitter and power relationships for both architectures, and the observed trends in jitter and power are explained and supported with calculations.