Design, Implementation, and Analysis of an Integrated Switched Capacitor Analog Neuron for Edge Computing AI Accelerators

Abstract

Parallel computing is the key to accelerate artificial neural networks, both in digital and analog implementations. Our research focuses on analog artificial neural networks (NN), where parallel computations are executed with voltages, charges and currents, using as the computing elements the same devices that act as memories for the raw processed data. These analog in-memory computing structures can be exploited for edge computing applications, thanks to their ability to directly interface with analog signals with low latency, reducing data throughput and front-end complexity. This work presents the specific implementation of a single neuron used in a larger feedforward, fully connected analog neural network ASIC (ANNA), showing its performance and criticalities. The ASIC is designed as a re-programmable analog accelerator for the reconstruction of the position of interaction of gamma rays in Anger cameras, for medical imaging applications as PET and SPECT. This first prototype has been fabricated on a 0.35 um CMOS process with an area of 24 mm2, and it is able to process 200,000 events per second, with an experimentally measured energy efficiency of 50 GOPS/W. The network has been trained on a Matlab model, that was adjusted to embed many nonidealities to match the physical chip, as demonstrated in this work.