A 3D Unified Analysis Method (3D-UAM) for Wafer-on-Wafer Stacked Near-Memory Structure

IF 3.1 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-03-16 DOI:10.1109/TVLSI.2025.3566468

Song Wang;Yixin Guo;Wei Tao;Xuerong Jia;Fujun Bai;Jie Tan;Yubing Wang;Liang Bai;Fuzhi Guo;Qi Liu;Jin Li;Peng Yin;Fenning Liu;Jing Liu;Xiaodong Long;Yanwu Han;Zhongcheng Yu;Mengzi Cheng;Song Chen;Xiping Jiang

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引用次数: 0

Abstract

The wafer-on-wafer (WoW) stacked structure exhibits pioneering advantages in near-memory computing but encounters challenges in 3D analysis due to the miniaturization of vertical connection structures and the simplification of vertical drivers. This article introduces a 3D unified analysis method (3D-UAM), which facilitates standard-cell-level signal integrity (SI) analysis across the 3D WoW stacked structure with hybrid processes, including a comprehensive 3D vertical connection theoretical model that bridges the dynamic random access memory (DRAM) and logic netlists. The accuracy of the 3D-UAM is confirmed through consistency analysis with the results of the 3D field model. The authenticity of the 3D-UAM is validated through correlation analysis with the physical test results from the WoW stacked DRAM test chip. The practicality of the 3D-UAM is demonstrated through channel optimization on a 20-layer DRAM WoW structure and power integrity (PI) analysis for the WoW stacked structure.

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片上堆叠近记忆结构的三维统一分析方法(3D- uam

晶圆对晶圆（WoW）堆叠结构在近内存计算方面具有开创性的优势，但由于垂直连接结构的小型化和垂直驱动器的简化，在3D分析方面面临挑战。本文介绍了一种3D统一分析方法（3D- uam），该方法促进了具有混合过程的3D WoW堆叠结构的标准单元级信号完整性（SI）分析，包括连接动态随机存取存储器（DRAM）和逻辑网络列表的综合3D垂直连接理论模型。通过与三维场模型结果的一致性分析，验证了3D- uam的准确性。通过与WoW堆叠式DRAM测试芯片物理测试结果的相关性分析，验证了3D-UAM的真实性。通过20层DRAM WoW结构的通道优化和WoW堆叠结构的功率完整性（PI）分析，证明了3D-UAM的实用性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.