A Supply Noise-Insensitive Ring DCO With a Self-Biased Shunt Regulator Array in Wide-Range Digital PLL

Abstract

This brief proposes a digital phase-locked loop (DPLL) with a power supply noise (PSN) regulated ring-type digitally controlled oscillator (DCO) using an nMOS shunt regulator array. The proposed nMOS array dynamically detects the PSN and creates a pathway, channeling the PSN forwarded through the digitally controlled resistor (DCR) directly to the ground. To support the proposed power supply noise compensation (PNC) technique in wide-range operation, the output bits from the digital loop filter (DLF) control not only the DCR but also the total transconductance of the nMOS array. The supply-sensing amplifier (SSA) between the supply and the gates of the nMOS array amplifies supply noise to lower the voltage headroom, allowing the DCO to run faster. Fabricated in 40-nm CMOS technology, the prototype DPLL demonstrates an rms jitter of 1.27 ps under 1 MHz, 20-mV_PP sinusoidal noise, while the rms jitter without the regulator is measured as 3.26 ps. The total power consumption and area occupation of the DPLL are 13.5 mW and 0.066 mm², respectively. The proposed scheme for PNC contributes only 1.90 mW and 0.0017 mm², representing 14.1% and 2.8% of the total, respectively.