A Featureless Dual-Mode Latch-Based PUF

IF 3.1 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-03-20 DOI:10.1109/TVLSI.2025.3565644

Ruikang Liu;Min Song;Changzhen Yu;Zhen Zhang;Wei Duan;Dawei Li;Ming Zhang;Meilin Wan

{"title":"A Featureless Dual-Mode Latch-Based PUF","authors":"Ruikang Liu;Min Song;Changzhen Yu;Zhen Zhang;Wei Duan;Dawei Li;Ming Zhang;Meilin Wan","doi":"10.1109/TVLSI.2025.3565644","DOIUrl":null,"url":null,"abstract":"Most physical unclonable functions (PUFs) can be located by attackers and are vulnerable to various physical attacks due to their distinct image and circuit features. To address this vulnerability, this article proposes a featureless dual-mode latch-based (FDL) PUF that is concealed within the digital circuit. The FDL PUF is implemented using standard cells and a digital design flow. It is then randomly distributed among other standard digital cells within the chip to eliminate possible identification of image features. Moreover, the output key of the FDL PUF is randomly extracted, and the FDL PUF is then repurposed to store other intermediate variables of the security algorithm, effectively eliminating the circuit features. The proposed FDL PUF is integrated into a secure identity authentication chip fabricated using a standard 0.18-<inline-formula> <tex-math>$\\mu $ </tex-math></inline-formula>m CMOS process. The feasibility of locating the FDL PUF units is evaluated using computer vision technologies, specifically YOLOv10 combined with OpenCV. Test results demonstrate that the number of suspected latch-based PUF units is approximately 15 times higher than the actual number of FDL PUF units for the test security chip, highlighting the significant challenge faced by attackers when attempting to locate the FDL PUF.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 8","pages":"2312-2323"},"PeriodicalIF":3.1000,"publicationDate":"2025-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/11007641/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}

引用次数: 0

Abstract

Most physical unclonable functions (PUFs) can be located by attackers and are vulnerable to various physical attacks due to their distinct image and circuit features. To address this vulnerability, this article proposes a featureless dual-mode latch-based (FDL) PUF that is concealed within the digital circuit. The FDL PUF is implemented using standard cells and a digital design flow. It is then randomly distributed among other standard digital cells within the chip to eliminate possible identification of image features. Moreover, the output key of the FDL PUF is randomly extracted, and the FDL PUF is then repurposed to store other intermediate variables of the security algorithm, effectively eliminating the circuit features. The proposed FDL PUF is integrated into a secure identity authentication chip fabricated using a standard 0.18-

$\mu $

m CMOS process. The feasibility of locating the FDL PUF units is evaluated using computer vision technologies, specifically YOLOv10 combined with OpenCV. Test results demonstrate that the number of suspected latch-based PUF units is approximately 15 times higher than the actual number of FDL PUF units for the test security chip, highlighting the significant challenge faced by attackers when attempting to locate the FDL PUF.

查看原文本刊更多论文

基于闭锁的无特征双模PUF

大多数物理不可克隆函数（physical unclable function, puf）由于具有独特的图像和电路特性，容易被攻击者定位，容易受到各种物理攻击。为了解决这个漏洞，本文提出了一种隐藏在数字电路中的无特征双模锁存器（FDL） PUF。FDL PUF使用标准单元和数字设计流程实现。然后将其随机分布在芯片内的其他标准数字单元中，以消除对图像特征的可能识别。此外，随机提取FDL PUF的输出密钥，然后将FDL PUF重新用于存储安全算法的其他中间变量，有效地消除了电路特征。所提出的FDL PUF集成到使用标准0.18- $\mu $ m CMOS工艺制造的安全身份认证芯片中。利用计算机视觉技术，特别是YOLOv10与OpenCV相结合，评估了定位FDL PUF单元的可行性。测试结果表明，可疑的基于锁存器的PUF单元的数量大约是测试安全芯片的FDL PUF单元的实际数量的15倍，这突出了攻击者在试图定位FDL PUF时面临的重大挑战。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.