Fast and low cost FPGA-based architecture for arrhythmia detection with CNN

Abstract

Deep Neural Networks have been applied in many fields and have exhibited extraordinary abilities. However, many challenges arise when dealing with embedded or low-resource computing architectures in different contexts like healthcare or IoT in Industry 4.0. In recent years, rapid growth has been seen in using machine learning techniques to interpret sensor data in healthcare applications. Convolutional Neural Networks (CNNs) are highly effective, but they have a significant drawback: they require large amounts of computational resources, usually available only “on the Cloud”. Edge and Fog nodes in healthcare applications (e.g. wearable sensors) are generally ill-suited to running CNN models with requirements like low computational resources, real-time execution, (very) low power consumption or low intrusiveness. In order to get through these difficulties, we propose a solution based on novel data-flow architectures and layer partitioning that enables fast classification in CNNs even when dealing with low resources. We apply our approach in developing a classifier (based on CNNs) for arrhythmia detection, which maintains good precision on low-power and low-cost FPGAs. We prove that the presented approach is general enough to distribute computation on parallel FPGAs too. Results show interesting performance improvements even when using low-resource hardware to implement the classifier.