Ribbon transistors that scale

IF 40.9 1区工程技术 Q1 ENGINEERING, ELECTRICAL & ELECTRONIC

Nature Electronics Pub Date : 2025-07-22 DOI:10.1038/s41928-025-01425-y

Katharina Zeissler

引用次数: 0

Abstract

The researchers — who are based at the Intel Foundry in Oregon, USA — developed a 180 nm cell height library for high-performance applications and a 160 nm cell height library for low-power applications. The contact resistance and device capacitance were reduced by integrating Backside PowerVia (Intel’s backside power delivery technology) and optimizing the transistor front side. Extreme-ultraviolet direct print patterning was used to reduce the total mask count.

Fischer and colleagues show that Intel 18A can perform better than previous technology based on fin field-effect transistors, Intel 3, with a frequency improvement of 18% and a power decrease of 38% at an iso-power of 0.75 V (and 25% and 36%, respectively, at 1.1 V). The technology also provides a 30% improvement in density scaling, with a bitcell area of 0.021 mm² for high-density cells and 0.023 mm² for high-current cells.

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带状晶体管

研究人员位于美国俄勒冈州的英特尔铸造厂，他们开发了用于高性能应用的180纳米单元高度库和用于低功耗应用的160纳米单元高度库。通过集成Backside PowerVia（英特尔的背面供电技术）和优化晶体管正面，降低了接触电阻和器件电容。采用极紫外直接印花图案，减少掩模总数。Fischer和他的同事们表明，Intel 18A的性能比之前基于翅片场效应晶体管Intel 3的技术更好，在0.75 V的等功率下，频率提高了18%，功耗降低了38%（在1.1 V时分别降低了25%和36%）。该技术还在密度缩放方面提高了30%，高密度电池的位电池面积为0.021 mm2，大电流电池的位电池面积为0.023 mm2。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Nature Electronics Engineering-Electrical and Electronic Engineering

CiteScore

47.50

自引率

2.30%

发文量

159

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