A phased-array transceiver in 65 nm CMOS for 6G

IF 40.9 1区工程技术 Q1 ENGINEERING, ELECTRICAL & ELECTRONIC

Nature Electronics Pub Date : 2025-07-22 DOI:10.1038/s41928-025-01426-x

Katharina Zeissler

引用次数: 0

Abstract

The researchers — who are based at the Institute of Science Tokyo, Panasonic Industry, Panasonic System Network R&D Lab, and Shinko Electric Industries — replace the oscillator buffer, which is typically used in such systems and has high power and chip area demands, with an injection-locked tripling phase shifter made using 65 nm node complementary metal–oxide–semiconductor (CMOS) technology. In addition to operating as a phase shifter, the device also functions as a frequency tripler. It is directly connected to the mixer to maximize the voltage amplitude and mixer input. An eight-element module with two transceiver integrated circuits, each with four transceivers, is shown to have a maximum data rate of 56 Gbps at a communication distance of 0.3 m and a 26 dBm effective radiated power at 154 GHz, while having a power consumption of up to 150 mW per element and an area of 8.4 mm × 20 mm.

Original reference: A 150 GHz high-power-density phased-array transceiver in 65nm CMOS for 6G UE module. In Proc. 2025 IEEE Symposium on VLSI Technology & Circuits (2025); https://www.vlsisymposium.org/

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6G的65纳米CMOS相控阵收发器

来自东京科学研究所、松下工业公司、松下系统网络研发实验室和新科电气工业公司的研究人员用一种采用65nm节点互补金属氧化物半导体（CMOS）技术制成的注入锁定三倍移相器取代了振荡器缓冲器，该缓冲器通常用于此类系统中，具有高功率和芯片面积需求。除了作为移相器外，该器件还可以作为三倍频器。它直接连接到混频器，以最大限度地提高电压幅值和混频器输入。采用两个收发器集成电路的八元模块，每个模块有四个收发器，在通信距离为0.3 m时具有56 Gbps的最大数据速率，在154 GHz时具有26 dBm的有效辐射功率，而每个单元的功耗高达150 mW，面积为8.4 mm × 20 mm。原始参考：用于6G UE模块的150 GHz高功率密度相控阵收发器。在Proc 2025 IEEE VLSI技术研讨会&；电路(2025);https://www.vlsisymposium.org/

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Nature Electronics Engineering-Electrical and Electronic Engineering

CiteScore

47.50

自引率

2.30%

发文量

159

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