FPGA-Based Design of Ultra-Efficient Approximate Adders for High-Fidelity Image Processing: A Logic-Optimized Approach

Abstract

Emerging as a promising paradigm for improving energy efficiency in error-tolerant applications including image processing, neural networks, and embedded vision systems is approximative computing. Most current approximative adder designs, however, either compromise output quality or show poor trade-off between logic complexity and computational accuracy. In order to close this gap, this work suggests a family of new 1-bit approximate full adder (AFA) designs optimized with basic AND-OR gate logic. While keeping reasonable error margins for real-time image processing, these approaches decrease device footprint and power consumption. Conventional and state-of-the-art approximate adders were compared against the proposed AFAs—AFA1, AFA2, and AFA3—on metrics including logic use, propagation delay, power dissipation, and Peak Signal-to-Noise Ratio (PSNR) in picture enhancement tasks. On an Intel Cyclone IV EP4CE115 FPGA, the AFAs attained up to 45.3% decrease in LUT utilization, 29.9% reduced power consumption, and 34.1% speed improvement over traditional full adders. The best-performing design (AFA3) in image addition studies produced a PSNR of 34.6 dB, therefore verifying good perceptual integrity appropriate for use in practical vision applications. This work provides a compact, energy-efficient design framework for digital image processing systems, therefore advancing the state of approximative arithmetic. Strong prospects for deployment in low-power, resource-constrained environments including IoT edge devices, and FPGA-based accelerators are the architectural simplicity and error-resilient behavior of the suggested adders.