Compact Geometric Feature Representation for Improved Capacitance Pattern-Matching in Parasitic Extraction

Abstract

The runtime and accuracy of interconnect parasitic extraction are becoming increasingly crucial for integrated circuit design in advanced manufacturing processes. In this study, we propose a novel method of capacitance matching that maps low-level features to high-level spaces, which reduces feature dimensions without losing essential information and provides a compact form for the geometric features of 2-D patterns in full-chip capacitance extraction. Furthermore, we are introducing a creative labeling strategy that eliminates the requirement for separate task-specific heads or different input representations. This innovative approach enables simultaneous data processing for both total and coupling capacitance tasks, leading to a significant reduction of complexities. Our experiments demonstrate that our entire feature representation and pattern-matching algorithm delivers exceptional accuracy, improved runtime, providing an efficient solution for large-scale capacitance extraction.