Circuit design of in-situ training memristive backpropagation neural network

Abstract

Memristive backpropagation (BP) neural network in-situ training is of significant importance for accelerating data processing. Currently, three main challenges hinder circuit design of the in-situ training memristive BP neural network: first, achieving circuit timing control without computer assistance is difficult; second, for the existing memristive BP neural network, it is hard to convert the change of weight values to memristance change; third, there is a lack of memristor control strategy suitable for in-situ training. To address the three challenges, this paper proposes a timing control method that does not require computer assistance, utilizing MOS transistors and analog value storage circuits to divide the training of the memristive BP neural network into four phases. Next, a novel memristor array is designed in which memristance correspond to the weight value linearly. Therefore, the weight change obtained by BP algorithm is convenient to be transferred as memristance change. Then, characteristics of the memristor are analyzed to map the memristance change as the corresponding control pulse. The amplitude of the control pulse are calculated by the multiplication and division circuit. Finally, XOR, iris classification, and MNIST digit classification experiments are conducted on the proposed memristive BP neural network circuit, proving that the proposed circuit design has good performance.