Performance enhancement of a spacer-engineered GS SOI n-FinFET with 10 nm gate length

Abstract

This study showcases the improvement in conventional SOI n-FinFET devices with the incorporation of a high-K spacer and gate stack (GS) engineering at 10 nm gate length. Three FinFET configurations were considered for comparison, and the simulated results show significant improvements in the analog and RF performance of the proposed configuration. Analog parameters such as the I_ON/I_OFF ratio increased almost 10⁴ times, subthreshold swing reduced by ∼60 %; transconductance increased by ∼92 %, QF improved by ∼382 %, TGF enhanced by ∼302 %, intrinsic gain increased by almost 8 times, and early voltage by almost 5 times, indicating the proposed device is suitable for high-performance CMOS circuits. Further, the RF analysis is performed with parameters like cut-off frequency, GFP, TFP, etc., exhibiting considerable improvement for the proposed configuration. Thus, gate stacking and spacer engineering significantly improve the FinFET performance, enhancing the analog and RF capabilities of semiconductor devices for more efficient integrated circuits.