A robust and efficient new paradigm for building in-memory stateful logic system with memristor: Based on multi-level co-optimization

Abstract

This paper introduces a new paradigm of memristor-based in-memory stateful logic computing. Based on multi-level co-optimization. In device level, with the aid of Mirrored RRAM Device (MRD), we develop a scheme to build basic logics by a single device in a reconfigurable manner. Furthermore, we also proposed a method for cascading logic to construct more complex logic. Compared to existing architectures, our MRD based method exhibits robustness against voltage and device variations, and eliminates the need for multiple reference voltages. Our method also support execution of more complex logic operations, such as 1-bit full adders, through a cascaded configuration in just three steps using four MRD devices. SPICE simulations have been conducted to validate the feasibility of our approach. These advancements position the MRD as a promising candidate for scalable and efficient in-memory computing applications.