Large-Area Geometric Diodes Based on Asymmetric and Nonlinear Transport in Patterned Graphene

Abstract

This contribution reports a comprehensive investigation into the development and validation of optimized models for simulating the electronic properties of large-scale graphene-based geometric diodes. Our study incorporates unique features as, for example, a general treatment for the boundary conditions, that include arbitrary impedance constrains for the diode output-terminals. The observed diode-like rectification behavior has its physical origin to be an intrinsic property of in the nonlinear carrier transport partial differential equations with polarity-dependent coefficients in asymmetric geometries. While atomistic methods offer, in principle, high accuracy at the atomic scale, their computational cost renders them impractical for simulating devices with dimensions exceeding a few nanometers. To address this limitation, we have developed an improved drift-diffusion framework that captures the essential physics of charge transport in the non-ballistic limit. Through extensive numerical simulations and new proposed diode topologies, we have investigated the impact of geometric parameters and external bias on the device characteristics. Direct quantitative comparison of independent results, obtained assuming fully coherent and fully diffusive transport in four-terminal diodes, has also been reported. The present model can be effectively used to preliminarily compare different diode geometries and to design/optimize large multi-terminal structures based on graphene.