Zexiang Zhang , Hong Rao , Shaoqing Jia , Huiling Feng , Shuanggen Liu
{"title":"PQES: Post-quantum encryption and signature scheme based on FFT-accelerated polynomial ring lattice for IoT devices","authors":"Zexiang Zhang , Hong Rao , Shaoqing Jia , Huiling Feng , Shuanggen Liu","doi":"10.1016/j.sysarc.2025.103515","DOIUrl":null,"url":null,"abstract":"<div><div>With the rapid advancement of quantum computing, traditional public-key cryptosystems (e.g., RSA and ECC) are facing severe threats from quantum attacks (e.g., Shor’s algorithm). To address the demand for efficient and secure communication in resource-constrained scenarios such as the Internet of Things (IoT), this paper proposes an integrated quantum-resistant encryption and signature scheme based on polynomial ring lattices and accelerated by the Fast Fourier Transform (FFT). The scheme combines the Ring Learning With Errors (Ring-LWE) and Ring-LWE-Short Integer Solution (Ring-SIS) problems, optimizing operations over the polynomial ring <span><math><mrow><msub><mrow><mi>Z</mi></mrow><mrow><mi>q</mi></mrow></msub><mrow><mo>[</mo><mi>x</mi><mo>]</mo></mrow><mo>/</mo><mrow><mo>(</mo><msup><mrow><mi>x</mi></mrow><mrow><mi>N</mi></mrow></msup><mo>+</mo><mn>1</mn><mo>)</mo></mrow></mrow></math></span> to significantly reduce key and ciphertext sizes. Additionally, FFT techniques are introduced to accelerate polynomial multiplication, while finite field FFT and floating-point error correction mechanisms address precision issues. Experimental results demonstrate that for polynomial degrees <span><math><mrow><mi>N</mi><mo>≥</mo><mn>1024</mn></mrow></math></span>, the encryption time is reduced by 23% compared to CRYSTALS-Kyber, with a 35% decrease in memory consumption. Moreover, Our signature verification mechanism demonstrates significantly lower resource consumption compared to both CRYSTALS-Dilithium and Falcon implementations under equivalent security parameters, making it suitable for low-overhead verification on edge devices and efficient signing on servers.</div></div>","PeriodicalId":50027,"journal":{"name":"Journal of Systems Architecture","volume":"167 ","pages":"Article 103515"},"PeriodicalIF":3.7000,"publicationDate":"2025-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Journal of Systems Architecture","FirstCategoryId":"94","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S1383762125001870","RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q1","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
With the rapid advancement of quantum computing, traditional public-key cryptosystems (e.g., RSA and ECC) are facing severe threats from quantum attacks (e.g., Shor’s algorithm). To address the demand for efficient and secure communication in resource-constrained scenarios such as the Internet of Things (IoT), this paper proposes an integrated quantum-resistant encryption and signature scheme based on polynomial ring lattices and accelerated by the Fast Fourier Transform (FFT). The scheme combines the Ring Learning With Errors (Ring-LWE) and Ring-LWE-Short Integer Solution (Ring-SIS) problems, optimizing operations over the polynomial ring to significantly reduce key and ciphertext sizes. Additionally, FFT techniques are introduced to accelerate polynomial multiplication, while finite field FFT and floating-point error correction mechanisms address precision issues. Experimental results demonstrate that for polynomial degrees , the encryption time is reduced by 23% compared to CRYSTALS-Kyber, with a 35% decrease in memory consumption. Moreover, Our signature verification mechanism demonstrates significantly lower resource consumption compared to both CRYSTALS-Dilithium and Falcon implementations under equivalent security parameters, making it suitable for low-overhead verification on edge devices and efficient signing on servers.
期刊介绍:
The Journal of Systems Architecture: Embedded Software Design (JSA) is a journal covering all design and architectural aspects related to embedded systems and software. It ranges from the microarchitecture level via the system software level up to the application-specific architecture level. Aspects such as real-time systems, operating systems, FPGA programming, programming languages, communications (limited to analysis and the software stack), mobile systems, parallel and distributed architectures as well as additional subjects in the computer and system architecture area will fall within the scope of this journal. Technology will not be a main focus, but its use and relevance to particular designs will be. Case studies are welcome but must contribute more than just a design for a particular piece of software.
Design automation of such systems including methodologies, techniques and tools for their design as well as novel designs of software components fall within the scope of this journal. Novel applications that use embedded systems are also central in this journal. While hardware is not a part of this journal hardware/software co-design methods that consider interplay between software and hardware components with and emphasis on software are also relevant here.